Semi-systolic array based motion estimation processor design

This paper presents a new VLSI architecture for full-search block matching algorithm. The proposed architecture has two specific features: (1) it lhas a processor element (PE) array which provides sufficient computational power, where PE's work in a semi-systolic style and (2) it contains stream memory banks which provide scheduled data flow to reduce idle operations within PE array. By exploiting broadcasting and local data communications, hardware efficiency of the proposed architecture can be up to 1O(P%, which outperforms those systolic-array solutions found in the literature.